Padmini Boreddy

 
mlrit 2094
Padmini Boreddy
Assistant Professor
Years
Electronics and Communication Engineering
b.padhmini462@gmail.com
8142268836
Full Time
9699-151223-114127
VLSI Design - M.Tech
B.Tech
M.Tech
Digital Design Using Verilog ET lab

DESIGN OF EFFICIENT 64-BIT BINARY COMPARATOR USING MODIFIED GATE DIFFUSION INPUT (M-GDI) LOGIC
IJEEC: INTERNATIONAL JOURNAL OF ELECTRICAL ELECTRONICS AND COMMUNICATION ISSN 2048 - 1069
Volume: 15 Issue: 22 l APRIL -2015 Page 5341-5347