V Jagadheesh

 
MLRIT2095
V Jagadheesh
Assistant Professor
Years
Electronics and Communication Engineering
jagadheesh712@gmail.com
9989238433
Full Time
0373-151223-140911
VLSI SYSTEM DESIGN
B.Tech
M.Tech

“Design and Implementation of Efficient Modulo 2n+1 Adder” volume 17, issue 6 of International Journal of Computational Engineering & Management.
http://www.ijcem.org/papers112014/ijcem_112014_04.pdf